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Description: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
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Size: 924 |
Author: 杨承凯 |
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Description: sdram的vhdl实现
本文介绍了sdram的控制时序特征，并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
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Size: 84842 |
Author: cxr |
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Description: sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
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Size: 6652 |
Author: hxwf801 |
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Description: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
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Size: 237546 |
Author: joucan |
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Description: SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
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Size: 3410 |
Author: 陈建勇 |
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Description: SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
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Size: 7694 |
Author: 陈建勇 |
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Description: 改成用philips的lpc2132来做控制,省去了SED1335和它配套的sdram-Replaced with the lpc2132 do philips control, eliminating the SED1335 and its supporting SDRAM
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Size: 748544 |
Author: linfengdu |
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Description: 实验源码是2410完全开发用的，通过此源码实验初学者可以一步步步入arm开发的殿堂。
源码包括：led点亮、key、stdio操作以及nand和sdram操作控制等。-Experimental source is fully developed by 2410, and through this source beginners can experiment step by step into the development arm of the hall. Source include: led lighting, key, stdio operations, as well as NAND and SDRAM operation control.
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Size: 334848 |
Author: kangyulu |
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Description: (1)个人针对atmel提供的运行于CPU内13k空间的ram的romboot修改而成。
(2)提供了IRQ和FIQ的测试工作；
(3)提供了对外部sdram的数据总线和地址总线的测试工作
(3）提供了对spi dataflash和nor flash的访问操作
(4)实现了romboot在spi dataflash和nor flash中的升级
(5)因为受编译后文件不能超过13kbytes的限制，采用条件编译的方法控制各个功能-(1) individuals provided for Atmel running on the CPU with 13k of ram space romboot modified form. (2) provides the IRQ and FIQ testing (3) provide for external SDRAM data bus and address bus of the test (3) provides a spi dataflash and visit nor flash operations (4) realize the romboot in spi dataflash and nor flash the upgrade (5) because of the compiled files should not exceed 13kbytes restrictions, conditions compiled using various functional control
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Size: 299008 |
Author: yan_jordan |
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Description: DEC5502_USB程序主要实现了与PC机应用程序之间的USB通讯，并根据PC机传来的指令进行相应的动作。
DEC5502_LED程序通过配置系统定时器和系统中断来控制指示灯D5和D1，并且通过D5和D1是否交替闪烁来达到测试系统定时器和系统中断的目的。
DEC5502_DARAM程序实现了对DSP的片上DARAM的读写访问。
DEC5502_DMA程序通过配置DMA通道实现片上DARAM与外扩SDRAM之间的数据传送。
DEC5502_UARTONCHIP程序实现了DSP片上UART与PC机的串行数据通讯。-DEC5502_USB procedures with the main PC application communication between the USB and PC machines in accordance with instructions from the corresponding action. DEC5502_LED procedure and system configuration of the system timer interrupt to control the indicator D5 and D1, and D1 through D5 are flashing alternately to achieve the test system and the system timer interrupt purposes. DEC5502_DARAM procedures realize the DSP chip s read and write access daram. DEC5502_DMA procedure to configure DMA channels daram realize on-chip and external expansion of the data transfer between SDRAM. DEC5502_UARTONCHIP procedures realize the DSP on-chip UART and PC-serial data communications.
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Size: 606208 |
Author: 王建毅 |
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Description: TS201上的多通道DMA控制源代码，包含SDRAM读写-TS201 on the multi-channel DMA control of source code, including SDRAM read and write
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Size: 2048 |
Author: 云 |
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Description: SDRAM IPCore控制程序源代码。
请问有无usb原码-SDRAM IPCore source code control procedures. I would like to ask whether the original code usb
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Size: 113664 |
Author: hyf |
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Description: 对vga接口做了详细的介绍，并且有一
·三段式Verilog的IDE程序，但只有DMA
·电子密码锁，基于fpga实现，密码正
·IIR、FIR、FFT各模块程序设计例程，
·基于逻辑工具的以太网开发，基于逻
·自己写的一个测温元件（ds18b20）的
·光纤通信中的SDH数据帧解析及提取的
·VHDL Programming by Example（McGr
·这是CAN总线控制器的IP核，源码是由
·FPGA设计的SDRAM控制器，有仿真代码
·xilinx fpga 下的IDE控制器原代码,
·用verilog写的，基于查表法实现的LO
·精通verilog HDL语言编- up:in STD_LOGIC
down:in STD_LOGIC
run_stop:in STD_LOGIC
wai_t: in std_logic_vector(2 downto 0)
lift:in std_logic_vector(2 downto 0)
ladd: out std_logic_vector(1 downto 0)
)
end control
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Size: 18683904 |
Author: liuzhou |
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Description: 基于verilog hdl的SDRAM控制代码-SDRAM-based control of the verilog hdl code
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Size: 6144 |
Author: wxd |
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Description: 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
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Size: 36864 |
Author: NOOW |
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Description: vhdl语言编写的fpga控制sdram的程序，包括仿真结果.-program of vhdl to control sdram in which includes the simulating results
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Size: 323584 |
Author: lmy |
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Description: 本代码是控制SDRAM的VHDL代码，几经优化现已趋近完美，里面主要用状态机实现，现封装为entity，便于调用模块-This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to call the module
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Size: 9216 |
Author: kaishi |
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Description: module sdram_test(
input clk_50m,
input reset_n,
//sdram control
output S_CLK, //sdram clock
output S_CKE, //sdram clock enable
output S_NCS, //sdram chip select
output S_NWE, //sdram write enable
output S_NCAS, //sdram column address strobe
output S_NRAS, //sdram row address strobe
output [1:0] S_DQM, //sdram data enable
output [1:0] S_BA, //sdram bank address
output [12:0] S_A, //sdram address
inout [15:0] S_DB //sdram data
)
-module sdram_test(
input clk_50m,
input reset_n,
//sdram control
output S_CLK, //sdram clock
output S_CKE, //sdram clock enable
output S_NCS, //sdram chip select
output S_NWE, //sdram write enable
output S_NCAS, //sdram column address strobe
output S_NRAS, //sdram row address strobe
output [1:0] S_DQM, //sdram data enable
output [1:0] S_BA, //sdram bank address
output [12:0] S_A, //sdram address
inout [15:0] S_DB //sdram data
)
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Size: 2787328 |
Author: Wen Jun Ying |
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Description: 按键控制led灯亮灭顺序，从左到右跑或者从右往左跑(Press button to control the LED lights on and off)
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Size: 5188608 |
Author: baby321
|
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Description: 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造；
支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较适合DDR入门使用(Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure;
Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry)
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Size: 20480 |
Author: 唛侬
|
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